The present invention relates generally to the data processing field, and more particularly, relates to a synchronous dynamic random access memory (SDRAM) address error detection method and apparatus for implementing address error detection.
Parity is commonly used on processor chip system busses to detect bus transaction errors and to improve system reliability. Recently, in some systems parity is being replaced with error correction codes (ECC). ECC allow both detection and correction of errors on processor chip system busses.
One common ECC method used is called Single Error Correct Double Error Detect (SECDED). As the name indicates, all single bit and double bit errors are detected and single bit errors are corrected.
Dynamic random access memory (DRAM) storage interfaces in high reliability systems, such as server computers, use ECC schemes, such as SECDED to detect and correct DRAM chip data bit failures. While known ECC schemes protect against data bit failures, these ECC schemes do not protect against addressing failures. A defect on the address net or connector to the DRAM or an address failure in the addressing distribution circuitry on the DRAM chip itself will result in fetching the wrong data from the wrong memory location. In this situation, the ECC will be fetched with its associated data and no error will be detected.
To protect against addressing errors, address parity is commonly used. When an addressing error is reported, processing is halted. Single bit memory cell fails should be correctable and the processor should continue to run. However, address parity cannot be simply stored as a single separate bit in the memory because a single bit fail in the address parity memory cell could not be distinguished from an addressing error.
Address parity is sometimes incorporated into the ECC scheme. For example, address parity is generated on the address used to write the data to the SDRAM, incorporated into the ECC scheme, and the ECC is stored with the data. When data is read from the DRAM, the address parity is recreated from the ECC bits read from the SDRAM and compared with the expected address parity. The expected address parity is generated from the address used to read the SDRAM. An addressing error is reported if the expected address parity does not match the address parity recreated from the ECC bits read from the SDRAM.
There are advantages of incorporating address error detection into the ECC scheme rather than storing address parity in an address parity memory cell in the SDRAM. Incorporating address error detection into the ECC scheme allows detection and correction of all single bit errors, including a single bit error in the ECC. Incorporating address parity into the ECC scheme enables reduction of the number of bits required to support both ECC and address error checking.
In computer system configurations, memory read data originates in a DRAM, is transferred to a memory control chip, and is passed from the memory control chip across a system bus to a processor. The DRAM connected to the memory control chip may be a cache or main memory. The delay of getting the data from the DRAM to the processor is part of memory read latency. Reducing memory read latency increases processor performance. If the data ECC scheme used on the memory interface and the processor bus is identical, latency can be reduced by not having to hold up data in the memory control chip to regenerate ECC before sending it to the processor. There is no need for address parity on the processor system bus, so processor bus ECC schemes do not include address parity. If the memory interface incorporates address parity into the ECC, the ECC must be regenerated before being sent on the system bus. This adds memory latency.
A need exists for an effective mechanism to protect against addressing failures. It is desirable to provide a synchronous dynamic random access memory (SDRAM) method and apparatus for implementing address error detection.
A principal object of the present invention is to provide a synchronous dynamic random access memory (SDRAM) method and apparatus for implementing address error detection. Other important objects of the present invention are to provide such SDRAM method and apparatus for implementing address error detection substantially without negative effect and that overcome many of the disadvantages of prior art arrangements.
In brief, synchronous dynamic random access memory (SDRAM) method and apparatus are provided for implementing address error detection. A predefined pattern is generated for a write burst to the SDRAM. The predefined pattern is dependent on a write address. A bit of the predefined pattern is sequentially stored into the SDRAM on each burst transfer of the write burst to the SDRAM. An expected pattern is generated from a read address for a read burst. The stored predefined pattern is retrieved during a read burst. The retrieved predefined pattern is compared to the generated expected pattern for identifying a type of an addressing error.
In accordance with features of the invention, a sequence of the compared stored predefined pattern is used to distinguish the difference between an addressing failure and an address parity memory cell failure. The predefined pattern is generated for a write burst to the SDRAM by calculating an odd address parity on the write address. If the odd address parity on the write address is a one, then a first predefined pattern, such as 10101010 is written one bit each transfer of the address parity memory cell during the transfer of the burst 8 write. If the odd address parity on the read address is a zero, then a second predefined pattern, such as 01010101 is written one bit each transfer of the address parity memory cell during the transfer of the burst 8 write. Alternatively, the predefined pattern is generated for a write burst to the SDRAM by calculating an error correction code (ECC) on the write address. For example, an ECC code is used on the write address with a property of single-bit correct, double-bit detect. This enables the detection of a stuck-at address line, while distinguishing the difference between an addressing failure and an address parity memory cell failure.